Apply for access

What is RISC-V?

RISC-V is an open standard Instruction Set Architecture (ISA) which enables the royalty free development of CPUs and a common software ecosystem to be shared across them. With over 65 billion RISC-V devices forecast by the middle of the decade, this is a massively growing and hugely exciting technology area. Following the community driven ISA standard, a very diverse set of CPUs have been, and continue to be, developed which are suited to a range of workloads.

In this testbed we aim to provide HPC code developers and data-scientists access to the latest RISC-V CPUs so that they can easily and conveniently experiment with the architecture for their workloads. Access to the testbed is free and intended as a research resource.

Physical and soft-core CPUs

This testbed contains a mixture of physical RISC-V CPUs and soft-cores. The later are software descriptions of the CPU core which are then used to configure an FPGA and for that to electronically represent the CPU of interest. Making available both physical and soft-core CPUs provides the best of both worths, more maturity for the physical cores and the ability to experiment with state-of-the-art implementations and/or tailour CPUs for the soft-cores.