Workshop details
Co-located with SC24, this is half day workshop is running in Atlanta, USA and will be on the afternoon of Monday the 18th of November, 2pm to 5:30pm.
The goal of this workshop is to continue building the community of RISC-V in HPC, sharing the benefits of this technology with domain scientists, tool developers, and supercomputer operators. RISC-V is an open standard Instruction Set Architecture (ISA) which enables the royalty free development of CPUs and a common software ecosystem to be shared across them. Following this community driven ISA standard, a very diverse set of CPUs and accelerators have been, and continue to be, developed which are suited to a range of workloads. Whilst RISC-V has become very popular already in some fields, and over thirteen billion RISC-V core have been shipped, to date it has yet to gain traction in HPC. However, there are numerous potential advantages that RISC-V can provide to HPC and, assuming the significant rate of growth of this technology to date continues, as we progress further into the decade it is highly likely that RISC-V will become more relevant and widespread for HPC workloads. Furthermore, recent advances in RISC-V make it a more realistic proposition for HPC workloads than ever before, and an example of this is the new commodity available hardware that we are seeing be released and made generally available.
Workshop schedule
| Time | Session | Speaker |
|---|---|---|
| 14:00 - 14:05 | Welcome and aims | Nick Brown |
| 14:05 - 14:40 | Keynote: Why I chose to built Esperanto’s AI and HPC accelerator around RISC-V (abstract) (slides) | Dave Ditzel |
| 14:40 - 14:50 | Vendor Lightning Talk: The InspireSemi next gen Thunderbird compute accelerator for HPC, AI, and graph analytics (abstract) (slides) | Doug Norton |
| 14:50 - 15:00 | Vendor Lightning Talk: The Tenstorrent Tensix architecture (abstract) | Eric Duffy |
| 15:00 - 15:30 | Coffee Break | |
| 15:30 - 15:50 | Presentation: HPC from the RISC-V International perspective (abstract) (slides) | Jeff Scheel |
| 15:50 - 16:10 | Research paper: Preparing for HPC on RISC-V: Examining Vectorization and Distributed Performance of an Astrophyiscs Application with HPX and Kokkos (abstract) | Patrick Diehl |
| 16:10 - 16:30 | Research paper: Top-Down Microarchitecture Analysis Approximation Based on Performance Counter Architecture for SiFive RISC-V Processors (abstract) | Chan-Yu Mou |
| 16:30 - 16:50 | Research paper: Web-Based Simulator of Superscalar RISC-V Processors (abstract) (slides) | Jiri Jaros |
| 16:50 - 17:10 | Research paper: Accelerating stencils on the Tenstorrent Grayskull RISC-V accelerator (abstract) (slides) | Nick Brown |
| 17:10 - 17:20 | Short paper: Development of Fedora Linux Distribution for RISC-V (RV64G) Architecture (abstract) | Surendra Billa |
| 17:20 - 17:30 | Vendor Lightning Talk: E4 Experience with RISC-V in HPC (abstract) | Daniele Gregori |