Workshop details
Co-located with SC25, this is half day workshop is running in St. Louis, USA and will be on the morning of Monday 17th of November 9:00am to 12:30pm in room 242.
The goal of this workshop is to continue building the community of RISC-V in HPC, sharing the benefits of this technology with domain scientists, tool developers, and supercomputer operators. RISC-V is an open standard Instruction Set Architecture (ISA) which enables the royalty free development of CPUs and a common software ecosystem to be shared across them. Following this community driven ISA standard, a very diverse set of CPUs and accelerators have been, and continue to be, developed which are suited to a range of workloads. Whilst RISC-V has become very popular already in some fields, and over sixteen billion RISC-V core have been shipped, to date it has yet to gain traction in HPC. However, there are numerous potential advantages that RISC-V can provide to HPC and, assuming the significant rate of growth of this technology to date continues, as we progress further into the decade it is highly likely that RISC-V will become more relevant and widespread for HPC workloads. Furthermore, recent advances in RISC-V make it a more realistic proposition for HPC workloads than ever before, and an example of this is the new commodity available hardware that we are seeing be released and made generally available.
Workshop schedule
| Time | Session | Speaker |
|---|---|---|
| 9:00 - 9:00 | Welcome | Nick Brown |
| 9:00 - 9:30 | Invited talk: Invited talk: Cuzco from Open-source to a High Performance Computing CPU Design (abstract) | Shashank Nemawarkarl |
| 9:30 - 9:40 | Short paper: Bridging Simulation and Silicon: A Study of RISC-V Hardware and FireSim Simulation (abstract) | Patrick Diehl |
| 9:40 - 9:50 | Short paper: Simulating Hybrid Analog + RISC-V Systems for HPC Applications (abstract) | Cameron Durbin |
| 9:50 - 10:00 | Short paper: Accelerating Gravitational N-Body Simulations Using the RISC-V-Based Tenstorrent Wormhole (abstract) | Jenny Lynn Almerol |
| 10:00 - 10:30 | Morning break | |
| 10:30 - 10:50 | Research paper: IzhiRISC-V - a RISC-V-based Processor with Custom ISA Extension for Spiking Neuron Networks Processing with Izhikevich Neurons (abstract) | Wiktor Jan Szczerek |
| 10:50 - 11:10 | Research paper: RISC-V Vectorization Coverage for HPC: A TSVC-Based Analysis (abstract) | Hung-Ming Lai |
| 11:10 - 11:30 | Research paper: A RISC-V Vector Extension for Multi-word Arithmetic (abstract) | Yunhao Lan |
| 11:30 - 11:50 | Research paper: Enabling the syscall_intercept library for RISC-V (abstract) | Petar Andrić |
| 11:50 - 12:10 | Research paper: Is RISC-V ready for High Performance Computing? An evaluation of the Sophon SG2044 (abstract) | Nick Brown |
| 12:10 - 12:20 | Short paper: Assessing a RISC-V Accelerator for Cross-Section Lookup in Chipyard (abstract) | Andrew Ledbetter |
| 12:20 - 12:30 | Short paper: Dyninst on the RISC-V: Binary Instrumentation in Support of Performance, Debugging, and Other Tools (abstract) | Cheng-Hsun Angus He |
| 12:30 | Workshop close |