EPCC RISC-V testbed team
EPCC RISC-V testbed team


  • Workshops

Important dates

  • Early Paper Deadline: 1st July 2024 (AoE)
  • Early Paper Notification: 21st July 2024
  • Main Paper Deadline: 9th August 2024 (AoE)
  • Main Author Notification: 6th September 2024
  • Camera ready papers: 27th September 2024
  • Workshop: Monday 18th 2pm to 5:30pm

To help with visa issues for some, we are triailing two paper submission phases, an early and main phase. Authors are welcome to submit to either of these, with the expectation being that most papers will be submitted to the main deadline but the early deadline will provide authors with some more time to arrange visas for the USA if required.

Workshop details

Co-located with SC24, this is half day workshop is running in Atlanta, USA and will be on the afternoon of Monday the 18th of November, 2pm to 5:30pm.

Workshop scope

The goal of this workshop is to continue building the community of RISC-V in HPC, sharing the benefits of this technology with domain scientists, tool developers, and supercomputer operators. RISC-V is an open standard Instruction Set Architecture (ISA) which enables the royalty free development of CPUs and a common software ecosystem to be shared across them. Following this community driven ISA standard, a very diverse set of CPUs have been, and continue to be, developed which are suited to a range of workloads. Whilst RISC-V has become very popular already in some fields, and over thirteen billion RISC-V core have been shipped, to date it has yet to gain traction in HPC.

However, there are numerous potential advantages that RISC-V can provide to HPC and, assuming the significant rate of growth of this technology to date continues, as we progress further into the decade it is highly likely that RISC-V will become more relevant and widespread for HPC workloads. Furthermore, recent advances in RISC-V make it a more realistic proposition for HPC workloads than ever before, and an example of this is the new commodity available hardware that we are seeing be released and made generally available.

The open and standardised nature of RISC-V means that the large, and growing community, can be involved in shaping the standard and tooling. This is important from two perspectives, firstly it is our opportunity in the HPC community to help shape the future of RISC-V to ensure that it is suitable for the next generation of supercomputers. Secondly, whilst there are a wide variety of RISC-V CPUs currently available, the standard nature of the tooling means that very often the same software ecosystem comprising the compiler, operating system, and libraries will run across these whilst requiring few changes.

This workshop aims to bring together those already looking to popularise RISC-V in the field of HPC with the supercomputing community at-large. By sharing benefits of the architecture, success stories, and techniques we hope to further popularise the technology and increase involvement by the community.

Call for papers - workshop topics

We invite submissions of high-quality, original research results and works-in-progress on RISC-V with a general connection to HPC. Topics of interest for this workshop include (but are not limited to):

  • Example use-cases and case-studies that use RISC-V
  • Lessons learnt from leveraging RISC-V in HPC
  • Industry papers exploring the use of RISC-V
  • The porting of codes to RISC-V
  • Novel hardware and accelerators built upon RISC-V
  • Tools and techniques to aid in the use of RISC-V for HPC
  • Developments in HPC libraries to port them to RISC-V
  • Enhancements to RISC-V to make the architecture more suited for HPC
  • Compiler and runtime support for RISC-V
  • The RISC-V ecosystem
  • Future gazing how RISC-V might evolve the HPC community
  • And anything else related to RISC-V and HPC!

Paper submission

Authors are invited to submit unpublished, original work. Accepted papers will appear in the IEEE SC workshop proceedings published by the ACM. Papers should be submitted in two categories, full papers which are between 6 and 10 pages and short papers which are up to 5 pages. Page counts include references and figures. All papers should be submitted via Linklings here

All papers should be formatted using the IEEE conference proceedings template, two-column, US letter size templates are agailable here


Organising committee

  • Nick Brown (EPCC at the University of Edinburgh)
  • David Donofrio (Tactical Computing Labs)
  • Teresa Cervero (BSC)
  • Michael Wong (Codeplay)
  • Daniele Gregori (E4 Computer Engineering)
  • Matthew Turner (Samsung)

Program committee

  • Oliver Perks (Rivos)
  • John Leidel (Tactical Computing Labs)
  • Maurice Jamieson (EPCC)
  • Ruyman Reyes (Codeplay)
  • Luis Plana (BSC)
  • Joseph Lee (EPCC)
  • Luc Berger-Vergait (Sandia National Laboratories)
  • Chris Taylor (Tactical Computing Labs)