EPCC RISC-V testbed team
EPCC RISC-V testbed team


  • Workshops

Workshop details

Co-located with SC 2023, this is a half day afternoon workshop is on Monday 13th November 2023 between 2pm and 5:3pm in room 507 of the Denver Convention Centre, USA

The goal of this workshop is to continue building the community of RISC-V in HPC, sharing the benefits of this technology with domain scientists, tool developers, and supercomputer operators. There are numerous potential advantages that RISC-V can provide to HPC and, assuming the significant rate of growth of this technology to date continues, as we progress further into the decade it is highly likely that RISC-V will become more relevant and widespread for HPC workloads. This workshop aims to bring together those already looking to popularise RISC-V in the field of HPC with the supercomputing community at-large. Sharing benefits of the architecture, success stories, and techniques we hope to further popularise the technology and increase involvement by the community in this exciting technology.

Workshop schedule

Time Session Speaker
14:00 - 14:05 Welcome and aims Nick Brown
14:05 - 14:40 Keynote: RISC-V Everywhere (abstract) (slides) Mark Himelstein
14:40 - 14:45 Vendor Lightning Talk: Esperanto Technologies ET-SoC for AI and ML Workloads (abstract) (slides) Lee Flanagin
14:45 - 14:50 Vendor Lightning Talk: The InspireSemi next gen Thunderbird compute accelerator for HPC, AI, and graph analyticsr (abstract) (slides) Doug Norton
14:50 - 14:55 Vendor Lightning Talk: SG2042 Empowering RISC-V in High-Performance Computing (abstract) Liuxi Yang
14:55 - 15:00 Vendor Lightning Talk: E4 Experience with RISC-V in HPC (abstract) (slides) Daniele Gregori
15:00 - 15:30 Coffee Break  
15:30 - 15:50 Research paper: An Empirical Comparison of the RISC-V and AArch64 Instruction Sets (abstract) (slides) Daniel Weaver
15:50 - 16:10 Research paper: Evaluating HPX and Kokkos on RISC-V Using an Astrophysics Application Octo-Tiger (abstract) Patrick Diehl
16:10 - 16:30 Research paper: Is RISC-V Ready for HPC Prime-Time: Evaluating the 64-Core Sophon SG2042 RISC-V CPU (abstract) (slides) Joseph Lee
16:30 - 16:50 Research paper: Short Reasons for Long Vectors in HPC CPUs: A Study Based on RISC-V (abstract) (slides) Pablo Vizcaino Serrano
16:50 - 17:10 Research paper: Automatic Generation of Micro-Kernels for Performance Portability of Matrix Multiplication on RISC-V Vector Processors (abstract) (slides) Francisco Igual
17:10 - 17:30 Research paper: Challenges and Opportunities in the Co-Design of Convolutions and RISC-V Vector Processors (abstract) (slides) Miquel Pericas