EPCC RISC-V testbed team
EPCC RISC-V testbed team


Co-located with HPC Asia 2024, this workshop will run between 08:30 and 12:30 on the morning of January 25th 2024 in Nagoya, Japan

Workshop details

The goal of this workshop is to continue building the community of RISC-V in HPC, sharing the benefits of this technology with domain scientists, tool developers, and supercomputer operators. RISC-V is an open standard Instruction Set Architecture (ISA) which enables the royalty free development of CPUs and a common software ecosystem to be shared across them. Following this community driven ISA standard, a very diverse set of CPUs have been, and continue to be, developed which are suited to a range of workloads. Whilst RISC-V has become very popular already in some fields, and in 2022 the ten billionth RISC-V core was shipped, to date it has yet to gain traction in HPC.

Workshop schedule

Time Session Speaker
09:00 - 09:10 Welcome and aims Michael Wong
09:10 - 09:50 Keynote: Rev: Scalable HPC Workload Simulation using RISC-V in SST (slides) John Leidel
09:50 - 10:00 SG2042 Empowering RISC-V in High-Performance Computing (slides) Wang Zihan
10:00 - 10:30 Break  
10:30 - 11:00 E4 Experience with RISC-V in HPC (slides) Daniele Gregori
11:00 - 11:20 The phenomenal pace of change making RISC-V more attractive for HPC (slides) Nick Brown
11:20 - 11:50 Lessons learned on Cell/B.E. for Hetero Programming Model, and alignments tweaks on RISC-V for Network speeds (slides) Akira Tsukamoto
11:50 - 12:25 Panel: Will 2024 be the year for RISC-V in HPC?  
12:25 - 12:30 Conclusions and next steps Nick Brown