EPCC RISC-V testbed team
EPCC RISC-V testbed team


  • Issues

Some of the hardware (e.g. Sophon SG2042 and Allwinner D1) within the testbed supports RISC-V V vector extension (RVV). Here we document and provide references for compiling code with vector instructions.

A major caveat is that the first ratified RVV is version 1.0 (spec), whereas the C920 and C906 cores in Sophon SG2042 and the Allwinner D1 SoCs were designed to support RVV 0.7.1 (spec). The two specs are similar but not compatible. For more information, see 1 2.

On riscv-login, the following compilers modules (see Getting Started) support RVV 0.7.1:

  • riscv64-linux/gnu-8.4-rvv
  • riscv64-linux/gnu-9.2-rvv
  • riscv64-linux/gnu-10.2-rvv

The following compiler modules support RVV 1.0

  • riscv64-linux/gnu-10.2-rvv
  • riscv64-linux/llvm-15.0
  • riscv64-linux/llvm-16.0

RVV 0.7.1

The simplest way to work with RVV 0.7.1 is in assembly language. The spec provides some examples of how to do so. Tests of memcpy and strcpy speeds on Allwinner D1 hardware using RVV 0.7.1 have been recorded here.


RVV 1.0

Due to the fact that RVV 1.0 is the ratified version, there is significantly more support by compilers. The latest LLVM compiler and toolchain provide support for vector intrinsics (v0.10)and auto-vectorization.



RVV rollback

We have introduced a tool to translate RVV 1.0 assembly code to 0.7, which is available for download here https://github.com/RISCVtestbed/rvv-rollback. It is tested for the following workflow:

This is tested for the following workflow:

  1. Clang 15.0 to compile .cpp source to RVV 1.0 .s
  2. RVV-rollback to translate RVV1.0 .s to RVV0.7 .s
  3. GCC 10.2 (Xuantie-900 linux-5.10.4 glibc gcc Toolchain V2.6.1 B-20220906) to assemble RVV0.7 .s to .o

The tool does not support some features introduced in v1.0, such as fractional LMUL and 64-bit elements.