Workshop details
Co-located with SC26, this is half day workshop is running in Chicago, USA and co-located with SC26.
The goal of this workshop is to continue building the community of RISC-V in HPC, sharing the benefits of this technology with domain scientists, tool developers, and supercomputer operators. RISC-V is an open standard Instruction Set Architecture (ISA) which enables the royalty free development of CPUs and a common software ecosystem to be shared across them. Following this community driven ISA standard, a very diverse set of CPUs and accelerators have been, and continue to be, developed which are suited to a range of workloads. Whilst RISC-V has become very popular already in some fields, and over sixteen billion RISC-V core have been shipped, to date it has yet to gain traction in HPC. However, there are numerous potential advantages that RISC-V can provide to HPC and, assuming the significant rate of growth of this technology to date continues, as we progress further into the decade it is highly likely that RISC-V will become more relevant and widespread for HPC workloads. Furthermore, recent advances in RISC-V make it a more realistic proposition for HPC workloads than ever before, and an example of this is the new commodity available hardware that we are seeing be released and made generally available.
Workshop schedule
| Time | Session | Speaker |
|---|---|---|
| 8:30 - 8:30 | Welcome | Nick Brown |
| 8:30 - 9:00 | Invited talk: HPC from the RISC-V International perspective (abstract) | Tom Gall |
| 9:00 - 9:20 | Research paper: A JIT framework for Implicit GEMM and FlashAttention Micro-Kernels in RISC-V (abstract) | Miquel Pericas |
| 9:20 - 9:40 | Research paper: Investigating ET-SoC-1 Vector and Parallel Performance with sGEMM (abstract) | Richard Neale |
| 9:40 - 9:50 | Short paper: Machine Learning-Based Performance Prediction for RISC-V Vector (RVV) Processors (abstract) | Peijun Li |
| 9:50 - 10:00 | Short paper: Hitting the Memory Wall: Why Cache Miss Tolerance Defines CPU Performance Now (abstract) | Mia Shu-Yu Chang |
| 10:00 - 10:30 | Morning break | |
| 10:30 - 10:40 | Short paper: Porting and Benchmarking Chapel on Emerging RISC-V Hardware: An HPC Viability Study (abstract) | Patrick Diehl |
| 10:40 - 11:00 | Research paper: A community developed simulator for the Tenstorrent Tensix architecture(abstract) | Daniyal Arshad |
| 11:00 - 11:20 | Research paper: Scale Up Platform Enabled by RISC – SUPER (abstract) | Ronald Minnich |
| 11:20 - 11:40 | Research paper: TSVC-RVV: A Diagnostic Extension of TSVC for Evaluating RISC-V Auto-Vectorization (abstract) | Hung-Ming Lai |
| 11:40 - 12:00 | Research paper: Accelerating Fast Fourier Transforms with the RISC-V Vector Extension (abstract) | Daniel Seibel |
| 12:00 | Workshop close |